The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventor hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. The present disclosure relates generally to aligning signals in a variable structure timing recovery system, and, more particularly, to phase offset estimation for systems using power savings standards such as Energy Efficient Ethernet (EEE).
In a system using EEE, levels of activity (such as amounts of data transmission) are monitored, and amounts of power that are provided to components within the system are adjusted accordingly. For example, when a device such as a computer is not active, a port on a switch corresponding to the computer may be powered down into a standby or a sleep mode, leading to savings in power consumption. The EEE control policy may determine when to enter an energy saving state and how long to remain in an energy saving state. After the sleep mode, the system is in a period of wake training mode. The wake training mode serves to transition the system from sleep mode to normal mode, during which the system transmits data. By the end of the wake training mode, the system needs to be ready to transmit data in a normal data transmission mode. Typically, the standard specifies a maximum amount of time to be spent in the wake training mode, requiring that the system be ready to transmit data in the normal mode within a predetermined amount of time after sleep mode.
During the sleep mode, signals in the system, such as a clock signal, may drift. When a clock signal drifts, the clock signal at the end of the sleep mode may have a frequency and/or phase offset from a reference clock signal. Upon exiting the sleep mode, the system needs to be ready to transmit data in a normal data transmission mode, or to update system parameters in an update mode for EEE. Thus, during a transition between the sleep mode to the normal or update mode (i.e., the wake training mode), it is important to recover the correct and consistent timing across all clock signals in the system such that all components of the system are compatible with one another. In addition, this timing recovery must be performed within a specified time period such as a maximum amount of time allowed to be spent in the wake training mode. One way to ensure the timing recovery is fast is to precisely monitor the frequency and phase offsets attributable to drift during the sleep mode. In this case, upon entry into the wake training mode, the precise estimates of both the frequency and phase offsets are readily available. However, depending on the cost efficiency of the offset monitors, monitoring both the frequency and phase offsets during the sleep mode may consume more power than desired.